1. Field of the Invention
The invention relates to generating a cell library and in particular to avoiding forbidden pitches for cells in the library based on a specific resolution enhancement technique (RET) and a lithography model, thereby significantly improving printed image quality.
2. Related Art
In designing an integrated circuit (IC), engineers typically rely upon computer aided design (CAD) tools to help create a circuit schematic design. To actually fabricate this circuit in a semiconductor substrate, the circuit must be translated into a physical representation, called a layout. In one design process, the CAD tools can access a cell library, wherein each cell can include the layout for a set of devices that implement a certain function.
After creation, the layout can be transferred onto a mask. A mask is generally created for each layer of the IC design. The mask can then be used to optically project the layout onto a silicon wafer coated with photoresist material. For each layer of the design, a light is shone on the mask corresponding to that layer. This light passes through the clear regions of the mask, whose image exposes the underlying photoresist layer, and is blocked by the opaque regions of the mask, leaving that underlying portion of the photoresist layer unexposed. The exposed photoresist layer is then developed. The end result is a wafer coated with a photoresist layer exhibiting the desired pattern, which defines the features of that layer. This process is repeated for each layer of the design.
In some circuits in which the size of the circuit features approach the optical limits of the lithography process, one or more resolution enhancement techniques can be used to improve the accuracy of the pattern transfer from the layout to the wafer. Specifically, as the size of integrated circuit features drops to 0.18 μ and below, the features can become smaller than the wavelength of the light used to create such features, thereby creating lithographic distortions when printing the features onto the wafer. Resolution enhancement techniques (RETs) can compensate for such lithographic distortions. Such resolution enhancement techniques (RETs) may include, for example, optical proximity correction, phase shifting, and off-axis illumination.
Optical proximity correction (OPC) applies systematic changes to geometries of the layout to improve the printability of a wafer pattern. Rule-based OPC can include rules to implement certain changes to the layout, thereby compensating for some lithographic distortions. Rule-based OPC features can include serifs, hammerheads, bias and assist bars. In model-based OPC, a real pattern transfer can be simulated (i.e. predicted) with a set of mathematical formulas (i.e. models). In model-based OPC, the edges of a feature in a layout can be dissected into a plurality of segments, thereby allowing these segments to be individually moved to correct for proximity effects.
In phase shifting, ultra-small features are generated by the destructive interference of light in adjacent, complementary pairs of phase shifters having opposite phase, e.g. 0 and 180 degrees. In one embodiment, the phase shifters can be formed on a phase shifting mask (PSM), which is used in conjunction with a trim mask that can define other features of the layout. In the PSM, complementary phase shifters are configured such that the exposure radiation transmitted by one shifter is 180 degrees out of phase with the exposure radiation transmitted by the other shifter. Therefore, rather than constructively interfering and merging into a single image, the projected images destructively interfere where their edges overlap, thereby creating a clear and very small image between the phase shifters.
The illumination that exposes the photoresist can be configured as on- or off-axis. A typical on-axis illumination configuration includes a single circular opening. Exemplary off-axis illumination configurations include dipole (two openings), quadrupole (four openings), and annular (donut shaped). In general, an on-axis illumination works well for designs having isolated features whereas off-axis illumination works well for designs having densely populated features.
Although significantly improving the wafer printability, these RETs can be pitch sensitive. Pitch can be defined as a distance between a centerline of one feature to the centerline of an adjacent feature. For example, referring to FIG. 1, the pitch of a design including features 101 and 102 can be represented by a distance 103.
Therefore, pitch is a relative measure of whether a design is characterized as having isolated features or densely populated features. Pitch can be represented as a ratio that compares the width of features to the space between the features. Thus, a 1:1 pitch may represent densely populated features whereas a 1:10 pitch may represent isolated features.
Unfortunately, when using a RET, certain pitches in a design may result in significant degradation of image quality. FIG. 2A illustrates a graph 200 plotting image quality using one RET versus pitch. In graph 200, a threshold 202 indicates a particular image quality (which could be measured by contrast, the size of a process window, the mask error factor, or other parameters) that can be deemed satisfactory by a wafer fabrication facility. Curve 201 shows that at approximately a 1:6 pitch, the image quality falls below threshold 202. Therefore, this pitch is called a “forbidden” pitch when using that RET.
Using each type of RET (or even configurations within one type of RET) may result in a different set of forbidden pitches. For example, FIG. 2B illustrates an exemplary graph 210 based on using another type of RET from that in FIG. 2A. Graph 210 indicates that using this other RET can result in multiple (i.e. two) forbidden pitches (curve 211 falls below threshold 202 at approximately 1:4 and 1:7). Note that the image quality using the RET of FIG. 2B is overall less than that provided by using the RET of FIG. 2A. However, the forbidden pitches associated with using the RET of FIG. 2B result in significantly less image quality degradation than the forbidden pitch associated with using the RET of FIG. 2A.
Image quality degradation could result in, for example, loss of feature density. Therefore, wafer fabrication facilities could decide to use the RET of FIG. 2B instead of that in FIG. 2A. In other words, certain fabrication facilities could conclude that the risk of having a severe forbidden pitch, such as that associated with the RET in FIG. 2A, in a design outweighs the printability benefits from using that RET. Therefore, wafer fabrication facilities may opt to not use such high risk RETs.
Another way of dealing with forbidden pitches is to limit allowable pitches in the library based on a plurality of design rules. Generally, process engineers manually generate these design rules based on empirical data. In this technique, library designers are not allowed to incorporate any forbidden pitches in the cells of the library. However, as noted above, one pitch may be a forbidden pitch using one type of RET, but not for another type of RET. Therefore, design rules for libraries can be overly aggressive for the actual RET being used, thereby potentially losing the printing benefits of using that RET.
Additionally, other factors in combination with the pitch can also affect the image quality. For example, two-dimensional (2D) factors such as the proximity, size, and/or shape of features near the feature of interest may affect image quality. For example, FIGS. 3A-3C respectively illustrate three features 301, 302, and 303 that are the same size and have the same pitch relative to other features in the design. However, depending on the RET being used, the image quality of features 301-303 when printed can be different. Current rule-based techniques cannot consider these 2D factors because the design rules precede library cell generation.
Therefore, a need arises for a technique to consider forbidden pitches during library cell generation in light of specific resolution enhancement techniques to be used.